1. Field of the Invention
The present invention relates to an over-power protection circuit, and more specifically, to an over-power protection circuit for self-excited power converter.
2. Description of Related Art
Various self-excited power converters have been widely used in desktop computers for providing regulated voltage and current. The self-excited half-bridge power converter is a main application circuit in the field of the self-excited power converter. FIG. 1 illustrates the topology of a conventional self-excited half-bridge power converter composed of a primary-side circuit, a main transformer T1, a secondary-side circuit, an over-power detecting circuit and a driving transformer T2. The primary-side circuit comprises a regulating capacitor C1, a regulating capacitor C2, an upper power transistor Q3, an upper driving circuit 32, a lower power transistor Q4, a lower driving circuit 42 and a blocking capacitor CB. The secondary-side circuit comprises an output inductor LO, an output capacitor CO, a voltage divider RO1 and RO2, a PWM (Pulse Width Modulation) controller 100 and a compensating network having a compensating resistor RC as well as a compensating capacitor CC. The over-power detecting circuit consists of a filtering diode 22, a filtering capacitor CPD, a voltage divider RP1 and RP2.
In the self-excited half-bridge power converter, the bipolar transistors (the upper power transistor Q3 and the lower power transistor Q4) with feature of high voltage are used as a power switch while the upper power transistor Q3 and the lower power transistor Q4 are driven by a self-excited driving way. Therefore the energy stored in the primary side is delivered to the output of the self-excited half-bridge power converter through the main transformer T1. The driving transformer T2 having the current transformer behavior achieves the self-excited driving. This driving method is also called the proportional drive.
FIG. 2A illustrates a schematic diagram of conventional self-excited half-bridge power converter during start-up. Referring to FIG. 3, a PWM controller 100 generates a high-level switching signal S2 to turn on a transistor Q2. A supply voltage VDD charges the winding N22B of the driving transformer T2 through a diode 12 and a resistor RD. Due to the same polarity of the winding N22B and N11A, the winding N11A induces a positive voltage so as to produce a base current IB3. The primary-side current IP=hfe×IB3 is generated because the base current IB3 is amplified by the power transistor, wherein the hfe is especially the current gain of the upper power transistor Q3.
FIG. 2B illustrates a schematic diagram of conventional self-excited half-bridge power converter during energy transferring. The upper power transistor Q3 is a high voltage transistor with smaller current gain hfe and it needs larger base current IB to be driven. The driving transformer T2 having current transformer behavior achieves the self-excited driving. The detecting winding NP of the driving transformer T2 is used for detecting the primary-side current IP of the main transformer T1. Through the turn ratio of the winding N11A and the detecting winding NP, we can get:
                              I          B                =                              I            P                    ×                                    N                              11                ⁢                A                                                    N              P                                                          (        1        )            The winding N11A is proportional to the detecting winding NP. The primary-side current IP flows through the detecting winding NP so that the larger current IB is obtained then the base current IB generates the larger primary-side current IP. The upper power transistor Q3 is totally turned on by such positive feedback mechanism. Referring FIG. 3, the switching signal S3 is at high level and the base current IB3×hfe>IP. Thus the main transformer T1 delivers the stored energy to the output of the self-excited half-bridge power converter.
Moreover, the winding N11B induces negative voltage and the lower power transistor Q4 is off due to the different polarity of the winding N22B and N11B of the driving transformer T2. The circulating direction of the primary-side current IP is from the positive terminal of the regulating capacitor C1 to the upper power transistor Q3 then through the detecting winding NP of the driving transformer T2 to the main transformer T1. The primary-side current IP further passes the blocking capacitor CB and then turns back to the negative terminal of the regulating capacitor C1. The stored energy in the input is transformed to the output by the main transformer T1.
In addition, the detecting winding NP of the driving transformer T2 is not only detecting the primary-side current IP but also having the output current information to limit the output current. Through the filtering diode 22 and the filtering capacitor CPD, we can get an over-power detecting voltage VPD:
                              V          PD                =                                            V              B                        ×                                          N                22                                            N                11                                              =                                    I              P                        ×                                          N                11                                            N                P                                      ×                          Z              B                        ×                                          N                22                                            N                11                                                                        (        2        )            The VB is the voltage across the winding N11A or N11B; the winding N11 is the winding N11A or N11B; the winding N22 is the winding N22A or N22B; the ZB is the input impedance of the upper power transistor Q3 and the lower power transistor Q4. We can get the over-power signal VOP from the over-power detecting voltage VPD through the voltage divider RP1 and RP2.
Referring to FIG. 3 and FIG. 2C, a schematic diagram of the conventional self-excited half-bridge power converter during the freewheeling, when the PWM controller 100 generates a logic high of the switching signal S2 and S1 that make transistor Q1 and Q2 on, the winding N22A and N22B of the driving transformer T2 are short circuit. Thus the winding N11A and N11B cannot induce the base current IB and the detecting winding NP also cannot detect the primary-side current IP. Therefore, the upper power transistor Q3 and the lower power transistor Q4 are off. Referring to FIG. 3, the switching signal S3 and S4 are low level. The main transformer T1 cannot deliver the power to the output of the self-excited half-bridge power converter.
Referring to FIG. 3, and FIG. 2D, a schematic diagram of the conventional self-excited half-bridge power converter during the energy transferring, the transistor Q1 is on as the PWM controller 100 outputs a high-level switching signal S1. Since the polarity of winding N22A and N11B of the driving transformer T2 is the same, the winding N11B induces the positive voltage for generating the base current IB4. Through the turn ratio of the winding N11B and the detecting winding NP, the larger base current IB4 is obtained. Thus the lower power transistor Q4 is totally turned on. Referring to FIG. 3, the switching signal S4 is high level and the base current IB4×hfe>IP and the main transformer T1 delivers the stored energy to the output of the self-excited half-bridge power converter.
Furthermore, the winding N11A induces a negative voltage and the upper power transistor Q3 is off due to different polarity the winding N22A and N11A of the driving transformer T2. The switching signal S3 is at low level and the lower power transistor Q4 is on. Thus the circulating direction of the primary-side current IP is from the positive terminal of the regulating capacitor C2 to the blocking capacitor CB then through the main transformer T1 to the detecting winding NP of the driving transformer T2. Next the primary-side current IP further passes the lower power transistor Q4 and then back to the negative terminal of the regulating capacitor C2. Therefore, the stored energy in the input is delivered to the output by the main transformer T1.
Referring to FIG. 3, the switching signal S2 is for the start-up signal in the PWM controller 100 of the conventional self-excited half-bridge power converter. The switching signal S1 is also for the start-up signal in the PWM controller 100 of the conventional self-excited half-bridge power converter. The switching signal S2 is at low level.
A schematic diagram of the PWM controller of the conventional self-excited half-bridge power converter is shown in FIG. 4. The PWM controller 100 comprises a PWM unit 110, an error amplifier 120, a comparator 130 and a timer 140. The PWM unit 110 further comprises two D flip-flop 1101 and 1102, an oscillator 1103, two NAND gates 1104, 1105, and a comparator 1106. The oscillator 1103 generates a saw-toothed signal VSAW and a clock signal CLK. The saw-toothed signal VSAW determines the switching frequency of the switching signal S1 and S2. The positive input of the error amplifier 120 is coupled to a reference voltage VR. The negative input of the error amplifier 120 is coupled to a feedback terminal FB for generating a compensating signal VCOM in response to a feedback signal VFB. The positive of the comparator 1106 is coupled to the output of the error amplifier 120 in response to the compensating signal VCOM. The negative of the comparator 1106 is coupled to the oscillator 1103 in response to the saw-tooth signal VSAW. The output of the comparator 1106 through D flip-flop 1101, 1102 and two NAND gates 1104, 1105 determines the pulse width of the switching signal S1 and S2.
For the sake of safety reasons, an over-power protection must be provided to protect both power converter itself and the system power. A limited output power is thus required for a power converter under the overload and short circuit conditions. The primary-side current IP is used to detect the output current. The over-power signal VOP will raise in response to the increase of the output current, the power and the primary-side current IP once the overload and short circuit conditions are happened.
The output of the comparator 130 and the reset input of the timer 140 are in a high level via comparison of the comparator 130 when the over-power signal VOP is higher than the threshold signal VT. In the meantime, the timer 140 starts to count. After a period of the delay time Td, the output of the timer 140 will produce a high-level latch signal LATCH that makes the switching signal S3 and S4 off through the internal protection circuit of the PWM controller. The object of the delay time Td is to avoid the fault condition caused by immediately load change. The delay time Td needs to be larger than the response time of dynamic load.
The output voltage VO and the feedback signal VFB from feedback terminal FB are reduced when the output of the self-excited power converter is short. Because the reference voltage VR is a constant voltage and the voltage difference between the feedback signal VFB and the reference voltage VR is too large so that the error amplifier 120 will output a larger compensating signal VCOM(A) to the comparator 1106 to amplify the feedback signal VFB and reference voltage VR. The compensating signal VCOM increases to VCOM(A). The output power will raise, and the compensating signal VCOM also increases to VCOM(A) when the over-load is happened. The output of the comparator 1106 through D flip-flop 1101, 1102 and two NAND gates 1104, 1105 generates the switching signal S1(A) and S2(A) in accordance with the compensating signal VCOM(A) and the sawtooth signal VSAW.
We know that from FIG. 3 it will generates the switching signal S3(A) and S4(A) with larger pulse width and increase the duty cycle of the upper power transistor Q3 and the lower power transistor Q4 when the pulse width of the switching signal S1(A) and S2(A) is smaller than the pulse width of the switching signal S1 and S2. In the meantime, the voltage waveform of the voltage VT1 across the main transformer T1 will transfer to the voltage waveform of the voltage VT1(A). The duty cycle of the voltage VT1(A) across the main transformer T1 is larger than the duty cycle of the voltage VT1 and this situation will prolong until the end of the delay time Td. The power switch of the power supply sustaining very large voltage and current stress is easy to get damage because it is difficult to control the over-power protection during the delay time Td.
As described above, the objective of the present invention is to provide an over-power protection apparatus for the self-excited power converter. Therefore, the constant current control and cycle-by-cycle current limit is achieved by the over-power protection apparatus to solve the above-mentioned question.